About Me:

Hello, welcome to my home page. I am an Assistant Professor in the Department of CSE, Indian Institute of Information Technology Guwahati. I have joined the institute on 10th August 2015. Previously I did my M.Tech and PhD in CSE from Indian Institute of Technology Guwahati, under the guidance of Prof. Hemangee K. Kapoor. My academic details are:

  1. PhD from Indian Institute of Technology Guwahati in 2016 (January). Thesis: "Effective Utilization of LLCs by Managing Associativity, Placement and Mapping" (LLC means Last Level Cache).
  2. M.Tech (in CSE) from Indian Institute of Technology Guwahati in 2010 (July).
  3. MSc in Computer Science from Assam University Silchar, Assam in 2007 (June).


I am an adventure loving person. I like cycling, trekking, road trip etc. It is my dream to travel all over India with my cycle and motorcycle :) . I also love to play badminton, football, and cricket.

Mountain View

Research Interests:

My current research focus is on Chip-multiprocessors (CMP), specifically the issues of Last Level Cache (LLC), Network on Chip (NoC) and DRAM Caches. Some of the issues are mentioned bellow:

  1. Performance enhancement of LLCs in Tiled Based CMPs (TCMP).
  2. Minimising the on-chip communication latency for TCMP.
  3. Energy consumption and temperature optimisation of LLC, NoC and DRAM caches.
  4. Smart replacement policies for different NUCA (Non Uniform cache Access) based cache memory architectures.
Some of the simulation tools require for my research are: GEMS, SIMICS, Gem5, Booksim, McPAT, CACTI, HotSpot, Garnet and Orion etc.

I did my MTech in formal verification. During my MTech I have designed a mathematical model for the multi-clock latency insensitive systems. I have plan to work on formal verifications for cache coherence protocols, used by the TCMP. Though I never did any research on Automata, TOC and Compilers but I always feel a strong bond with these subjects.

Research Project: One of my project entitled, "Reducing Energy Consumption and Operating Temperature of Last Level DRAM Cache in Multicore Systems" has been approved by the Govt. of India, Science and Engineering Research Board (SERB), under the Early Career Research Award scheme. It will be a three years project.

Teaching:

Teaching is my passion and students feedback of my teaching is very important for me. I have taught the following courses in IIIT Guwahati with highly positive feedback from students.

  1. Compilers (CS320) and Compilers Lab (CS321)
  2. DBMS (CS240) and DBMS Lab (CS241)
  3. Theory of Computation (CS301).
  4. Advance Architecture (CS414).

Publications:

Journals
  1. Shirshendu Das and H. K. Kapoor, “Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets,” IEEE Transactions on Parallel and Distributed Systems (TPDS), accepted in January 2017.
  2. Shirshendu Das and H. K. Kapoor, “A Framework for Block Placement, Migration and Fast Searching in Tiled-DNUCA Architecture,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 22(1), 2016.
  3. Shirshendu Das and H. K. Kapoor, “Victim Retention for Reducing Cache Misses in Tiled Chip Multiprocessors,” Journal of Microprocessors and Microsystems (Elsevier), 38 (4), (2014), 263–275.
  4. Shirshendu Das, P. S. Duggirala, and H. K. Kapoor, “A formal framework for interfacing mixed-timing systems,” Integration, the VLSI Journal (Elsevier), 46 (3), (2013). 255-264.
  5. H. K. Kapoor, P. Kanakala, M. Verma, and S. Das, “Design and formal verification of a hierarchical cache coherence protocol for noc based multiprocessors,” The Journal of Supercomputing (Springer), 65 (2), 2013, 771-796.
Conferences
  1. Shirshendu Das and Hemangee K. Kapoor, "Latency Aware Block Replacement for L1 Caches in Chip MultiProcessors," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Bochum, Germany.
  2. Shirshendu Das and Hemangee K. Kapoor, "Dynamic Associativity Enabled DNUCA to Improve Block Localisation in Tiled CMPs," 31st ACM/SIGAPP Symposium On Applied Computing (SAC), 2016, Pisa, Italy.  
  3. Shounak Chakraborty, Shirshendu Das and Hemangee Kapoor, "Static Energy Efficient Cache Reconfiguration for Dynamic NUCA in Tiled CMPs," 31st ACM/SIGAPP Symposium on Applied Computing (SAC), 2016, Pisa, Italy.
  4. Shirshendu Das and Hemangee K. Kapoor, "Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches," 29th International Conference on VLSI Design-2016 (VLSID), 2016, Kolkata, India.
  5. Shounak Chakraborty, Shirshendu Das and Hemangee K. Kapoor, "Performance constrained static energy reduction using way-sharing target-banks," 17th Workshop on Advances on Parallel and Distributed Processing Symposium (APDCM), in conjunction with IPDPS, 2015, Hydrabad, India.
  6. Shirshendu Das and Hemangee K. Kapoor, "Dynamic Associativity Management Using Utility Based Way-Sharing," 30th ACM/SIGAPP Symposium On Applied Computing (SAC), 2015, Salamanca, Spain.
  7. Hemangee Kapoor, Shirshendu Das and Shounak Chakraborty, "Static energy reduction by performance linked cache capacity management in Tiled CMPs," 30th ACM/SIGAPP Symposium on Applied Computing SAC), 2015, Salamanca, Spain.
  8. Shirshendu Das and Hemangee K. Kapoor, "Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs," 28th International Conference on VLSI Design (VLSID), 2015, Bangalore, India.
  9. Mojjada Lakshmi Prasad, Shirshendu Das and Hemangee K. Kapoor, "An Approach for Multicast Routing in Networks-on-Chip," 13th International Conference on Information Technology (ICIT), 2014, Bhubaneswar, India.
  10. Prateek D. Halwe, Shirshendu Das, Hemangee K. Kapoor, "Towards a Better Cache Utilization Using Controlled Cache Partitioning," 11th IEEE International Conference on Embedded Computing (EmbeddedCom), 2013, Chengdu, China. 
  11. S. Das and H. K. Kapoor, "Dynamic associativity management using fellow sets," 4th International Symposium on Electronic System Design (ISED), 2013, NTU, Singapore 

Dr. Shirshendu Das

Assistant Professor (CSE)

Placement Coordinator

IIIT Guwahati

GNB Road, Ambari

Guwahati 781001

shirshendu[at]iiitg.ac.in

+919435277250