About
am an Assistant Professor in the Department of Electronics and Communications Engineering (ECE) at the Indian Institute of Information Technology Guwahati (IIITG) working from July, 2019. Prior to that, I received the Ph.D. degree in VLSI Design from the Indian Institute of Technology Guwahati (IITG). My research interests are on VLSI Design for Digital/Analog/Mixed-Signal Systems. For more information, please visit my homepage (Link)
Research Interests
Low-power Transceiver (Baseband/RF) Design, VLSI for Signal Processing and Communications, Analog and Mixed-Signal Circuit Design
Teaching
At IIITG, I have taught the following courses:
EC 101: Digital Design
EC 103: Basic Electronic Circuits
EC 241: Signals and Systems
EC 361: VLSI Design
EC 110: Digital Design LabEC 111: Basic Electronics Lab
EC 244: Digital Signal Processing Lab
EC 302: Analog Integrated Circuit Lab
EC 362: VLSI Design Lab
EC 661: VLSI Circuits and Systems
EC 672: Semiconductor Device Modeling
EC 662: VLSI CAD Lab
EC668: VLSI Solid State Circuits Lab
Research Grant
- VRITIKA, SERB (AV/VRI/2022/0217): Towards VLSI and Embedded System Design using FPGA Boards, 2022 (1,50,000)
Publication
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Conference
- S. Singh, S. Patel, S. Kumar, M. Das and B. Jajodia, "FPGA-Optimized Eight-Term Karatsuba Multiplications for Large Integer Multiplications", 2024 IEEE International Conference on Recent Innovation in Smart and Sustainable Technology (ICRISST), (2024), pages. 1-6, Presidency University, Itgalpura, Rajanukunte, Yelakhana, Bangalore, Karnataka,, India
- S. Kumar, S. Patel, S. Singh, M. Das and B. Jajodia, "Design and Evaluation of FPGA-Optimized Symmetrical Three-Term Karatsuba Multipliers", 2024 IEEE International Conference on Recent Innovation in Smart and Sustainable Technology (ICRISST), (2024), pages. 1-6, Presidency University, Itgalpura, Rajanukunte, Yelakhana, Bangalore, Karnataka,, India
- S. Kumar, S. Patel, S. Singh, M. Das and B. Jajodia, "FPGA-Optimized Two-Term Karatsuba Multiplications for Large Integer Multiplications", 2024 11th IEEE International Conference on Signal Processing and Integrated Networks (SPIN), (2024), pages. 1-6, ASET, Amity University, Sec-125, Noida, Delhi-NCR, India
- S. Singh, S. Patel, S. Kumar, M. Das and B. Jajodia, "An Eight-Term Karatsuba Multiplier for Cryptographic Hardware Primitives on FPGAs", 2024 3rd IEEE International Conference on Advancement in Electrical and Electronic Engineering (ICAEEE), (2024), pages. 1-6, Dhaka University of Engineering & Technology (DUET), Gazipur, Bangladesh
- R. Maharana, M. Das and B. Jajodia, "Design and Evaluation of FPGA-Optimized Asymmetrical and Symmetrical Five-Term Karatsuba Multipliers", 2024 3rd IEEE International Conference on Advancement in Electrical and Electronic Engineering (ICAEEE), (2024), pages. 1-6, Dhaka University of Engineering & Technology (DUET), Gazipur, Bangladesh
- Jitesh Lalwani, Dana Linnet, Babita Jajodia, Mandaar B. Pande, Amit Patel, Kshitij Dave and B R Nikilesh, "Efficient Earth Observation Satellites Mission Planning with Quantum Algorithm", 2024 Second IEEE International Conference in Trends in Quantum Computing & Emerging Business Technologies (TQCEBT), (2024), pages. 1-6, Christ (Deemed to be University), Pune Lavasa Campus, Pune, India
- Jitesh Lalwani, Dana Linnet, Babita Jajodia, Mandaar B. Pande, Amit Patel, Kshitij Dave and B R Nikilesh, "Efficient Earth Observation Satellites Mission Planning with Quantum Algorithm", 2024 Second IEEE International Conference in Trends in Quantum Computing & Emerging Business Technologies (TQCEBT), (2024), pages. 1-6, Christ (Deemed to be University), Pune Lavasa Campus, Pune, India
- M. Thakare and B. Jajodia, "Hardware Implementation for Determining Perfect and Non-Perfect Square Roots using Dwandwa Yoga on FPGA", in 2022 IEEE International Conference on Electrical, Computer and Energy Technologies (ICECET), (2022), Prague, Czech Republic
- P. Das and B. Jajodia, "Design Automation of Two-Stage Operational Amplifier Using Multi-Objective Genetic Algorithm and SPICE Framework", in 2022 IEEE 5th International Conference on Inventive Computation Technologies (ICICT), Lalitpur, Nepal, 20-22 July, (2022),
- V. Mishra, D. Pandey, S. Singh, S. Satapathy,, K. Goswami, B. Jajodia and D.S. Banerjee, "ART-MAC: An Approximate Rounding and Truncation Based MAC Unit for Fault-Tolerant Applications", in 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, Texas, USA, 28 May-June 1,, (2022),
- S. Singh, V. Mishra, S. Satapathy, D. Pandey, K. Goswami, D.S. Banerjee and B. Jajodia , "EFCSA: An Efficient Carry Speculative Approximate Adder with Rectification", in 2022 IEEE 23rd International Symposium on Quality Electronic Design (ISQED), San Jose, California, USA, 6-8 April, (2022),
- D. Pandey, V. Mishra, S. Singh, S. Satapathy, B. Jajodia and D.S. Banerjee, "HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications", in 2022 IEEE 23rd International Symposium on Quality Electronic Design (ISQED), San Jose, California, USA, 6-8 April, (2022),
- P. Yash, M. Thakare and B. Jajodia, "Optimized Hardware Implementation of Vedic Binary Multiplier using Nikhilam Sutra on FPGA", in 2022 IEEE 13th Latin American Symposium on Circuits and Systems (LASCAS), Puerto Varas, Chile, 1-4 March, (2022),
- S. Jakhodia and B. Jajodia, "Numerical Methods for Solving High-Order Mathematical Problems Using Quantum Linear System Algorithm on IBM QISKit Platform", in 2022 IEEE 3rd International Conference on Innovative Trends in Information Technology (ICITIIT), (2022), pages. 1-7, Virtual Mode
- M.Das and B.Jajodia, "Hardware Design of Optimized Large Integer Schoolbook Polynomial Multiplications on FPGA", 2022 19th IEEE International SoC Conference (ISOCC), , (2022), pages. 1-2, Lakai Sandpine Resort, Gangneung-si, Gangwon-do, Korea
- M. Karthik, J. Lalwani and B. Jajodia, "Quantum Text Teleportation Protocol for Secure Text Transfer by using Quantum Teleportation and Huffman Coding", 2022 IEEE International Conference in Trends in Quantum Computing & Emerging Business Technologies, (2022), pages. 1-6, Christ (Deemed to be University), Pune Lavasa Campus, 13-15 October,2022
- A. Chandra, J. Lalwani and B. Jajodia, "Towards an Optimal Hybrid Algorithm for EV Charging Stations Placement using Quantum Annealing and Genetic Algorithms", 2022 IEEE International Conference in Trends in Quantum Computing & Emerging Business Technologies, (2022), pages. 1-6, Christ (Deemed to be University), Pune Lavasa Campus, 13-15 October,2022
- M. Karthik, J. Lalwani and B. Jajodia, "Quantum Image Teleportation Protocol (QITP) and Quantum Audio Teleportation Protocol (QATP) by using Quantum Teleportation and Huffman Coding", 2022 IEEE International Conference in Trends in Quantum Computing & Emerging Business Technologies, (2022), pages. 1-6, Christ (Deemed to be University), Pune Lavasa Campus, 13-15 October,2022
- M.Das and B.Jajodia, "FPGA Implementation of Hybrid Karatsuba Multiplications for NIST Post-Quantum Cryptographic Hardware Primitives", 2022 19th IEEE International SoC Conference (ISOCC), , (2022), pages. 1-2, Lakai Sandpine Resort, Gangneung-si, Gangwon-do, Korea
- J. Bajaj and B. Jajodia , "Efficient Hardware Implementation of High-Speed Recursive Vedic Squaring Architecture on FPGA", in 2021 IEEE International Conference on Electrical, Computer and Energy Technologies (ICECET), Cape Town, South Africa, (2021), pages. 1-6,,
- M. Thakare, P. Yash, D. Chakraborty and B. Jajodia , "Efficient Hardware Implementation of Cube Architecture using Yavadunam Sutra on FPGA", in 2021 IEEE 64th International Midwest Symposium on Circuits and Systems (MWSCAS), (2021), pages. 373-376,
- R. Thombre and B. Jajodia , "Experimental Analysis of Attacks on RSA & Rabin Cryptosystems using Quantum Shor’s Algorithm", n Proceedings of International Conference on Women Researchers in Electronics and Computing (WREC), AIJR Proceedings, (2021), pages. 581-590, (Best Paper Award)
- J. Bajaj and B. Jajodia , "Squaring Technique using Vedic Mathematics", in Proceedings of International Conference on Women Researchers in Electronics and Computing (WREC), (2021), pages. 591-600, AIJR Proceedings
- B. Jajodia , S.R. Ahamed and A. Mahanta, "Demodulation techniques for IEEE 802.15.6 IR-UWB DBPSK WBAN transceivers", in IEEE 3rd International Conference on Smart Instrumentation, Measurement and Applications (ICSIMA), Putrajaya Marriott Hotel, Malaysia, (2015), pages. 1-5,
- B. Jajodia , S.R. Ahamed and A. Mahanta, "PPM Demodulation Schemes for IEEE 802.15.6 IR-UWB WBAN Receivers", in IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems (SPICES), (2015), pages. 1-5, NIT Calicut, India
- B. Jajodia , A. Mahanta and S.R. Ahamed, "A Six-Segment SRRC Pulse Generator for IEEE 802.15.6 WBAN Standard", n BODYNETS 2014 - 9th International Conference on Body Area Networks, Senate House, London, Great Britain, (2014), pages. 46-49,
Journal
- M. Das and B.Jajodia, "Area and Delay Trade-Offs in Three-Way Toom-Cook Large Integer Multipliers Implemented on FPGAs", IEEE Transactions on Circuits and Systems I: Regular Papers, (2024), pages. 1-10, IEEE
- B. Jajodia , A. Mahanta and S.R. Ahamed, "Energy-efficient DAC switching technique for single-ended SAR ADCs", AEU- International Journal of Electronics and Communications,Vol. 124, (2020), pages. 153334, Elsevier
- B. Jajodia , A. Mahanta and S.R. Ahamed, "IEEE 802.15.6 WBAN Standard Compliant IR-UWB Time-Hopping PPM Transmitter using SRRC signaling pulse", AEU- International Journal of Electronics and Communications,Vol. 117, (2020), pages. 153119, Elsevier
- B. Jajodia , A. Mahanta and S.R. Ahamed, "Mixed-Signal Demodulator for IEEE 802.15.6 IR-UWB WBAN Energy Detection based Receiver", IET Circuits, Devices & Systems,Vol. 12, No. 5, (2018), pages. 523-531,
Book Chapters
- S. Jakhodia, D. Singh and B. Jajodia, "Experimental Evaluation of QFT Adders on IBM QX Hardware", 2nd International Conference on Emerging Technologies for Computing, Communication and Smart Cities (ETCCS), Lecture Notes in Electrical Engineering,vol. 875, (2022), pages. 419-435, Springer, Singapore,Print ISBN: 978-981-19-0283-3, Online ISBN: 978-981-19-0284-0
- D. Singh, S. Jakhodia and B. Jajodia,Smys S., Balas V.E., Palanisamy R, "Experimental Evaluation of Adder Circuits on IBM QX Hardware", Inventive Computation and Information Technologies (ICICIT). Lecture Notes in Networks and Systems,vol. 336, (2022), pages. 333-347, Springer, Singapore,Print ISBN: 978-981-16-6722-0, Online ISBN: 978-981-16-6723-7
Others
- P. Das and B. Jajodia, "Design Optimization of Analog Circuit using Multi-Objective Genetic Algorithm and SPICE Framework", in North-East Research Conclave, Indian Institute of Technology Guwahati, (2022), (Technical Presentation on Extended Abstract)
Posters
- D. Pandey, V. Mishra, S. Singh, S. Satapathy and B. Jajodia, "HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications", in 28th IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC) Student Research Symposium (SRS), Bengaluru, Karnataka, (2021), (Best Poster Award)