About:

I am an Assistant Professor in the Department of Electronics and Communications Engineering (ECE) at the Indian Institute of Information Technology Guwahati (IIITG) working from July, 2019. Prior to that, I received the Ph.D. degree in VLSI Design from the Indian Institute of Technology Guwahati (IITG). My research interests are on VLSI Design for Digital/Analog/Mixed-Signal Systems. For more information, please visit my homepage (Link)

Research Interests:

VLSI Design on Analog/Digital/Mixed-Signal Systems, RISC Processor Design, Quantum Computing

Teaching:

At IIITG, I have taught the following courses:

  • EC 103: Basic Electronic Circuits
  • EC 241: Signals and Systems
  • EC 361: VLSI Design
  • EC 110: Digital Design Lab
  • EC 111: Basic Electronics Lab
  • EC 244: Digital Signal Processing Lab
  • EC 302: Analog Integrated Circuit Lab
  • EC 362: VLSI Design Lab
  • EC 661: VLSI Circuits and Systems
  • EC 672: Semiconductor Device Modeling
  • EC 662: VLSI CAD Lab

Publications:

Journals
  1. B. Jajodia , A. Mahanta and S.R. Ahamed, “Energy-efficient DAC switching technique for single-ended SAR ADCs”, AEU- International Journal of Electronics and Communications, Elsevier, Vol. 124, Page-153334, 2020
  2. B. Jajodia , A. Mahanta and S.R. Ahamed, “IEEE 802.15.6 WBAN Standard Compliant IR-UWB Time-Hopping PPM Transmitter using SRRC signaling pulse”, AEU- International Journal of Electronics and Communications, Elsevier, Vol. 117, Page-153119, 2020
  3. B. Jajodia , A. Mahanta and S.R. Ahamed, “Mixed-Signal Demodulator for IEEE 802.15.6 IR-UWB WBAN Energy Detection based Receiver”, IET Circuits, Devices & Systems, Vol. 12, No. 5, pp. 523-531, Sept. 2018
Conferences
  1. M. Thakare and B. Jajodia , "Hardware Implementation for Determining Perfect and Non-Perfect Square Roots using Dwandwa Yoga on FPGA”, in 2022 IEEE International Conference on Electrical, Computer and Energy Technologies (ICECET), Prague, Czech Republic, 20-22 July, 2022
  2. P. Das and B. Jajodia , "Design Automation of Two-Stage Operational Amplifier Using Multi-Objective Genetic Algorithm and SPICE Framework," in 2022 IEEE 5th International Conference on Inventive Computation Technologies (ICICT), Lalitpur, Nepal, 20-22 July, 2022
  3. V. Mishra, D. Pandey, S. Singh, S. Satapathy,, K. Goswami, B. Jajodia and D.S. Banerjee, "ART-MAC: An Approximate Rounding and Truncation Based MAC Unit for Fault-Tolerant Applications", in 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, Texas, USA, 28 May-June 1, 2022
  4. S. Singh, V. Mishra, S. Satapathy, D. Pandey, K. Goswami, D.S. Banerjee and B. Jajodia , "EFCSA: An Efficient Carry Speculative Approximate Adder with Rectification", in 2022 IEEE 23rd International Symposium on Quality Electronic Design (ISQED), San Jose, California, USA, 6-8 April, 2022
  5. D. Pandey, V. Mishra, S. Singh, S. Satapathy, B. Jajodia and D.S. Banerjee, "HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications", in 2022 IEEE 23rd International Symposium on Quality Electronic Design (ISQED), San Jose, California, USA, 6-8 April, 2022
  6. P. Yash, M. Thakare and B. Jajodia , “Optimized Hardware Implementation of Vedic Binary Multiplier using Nikhilam Sutra on FPGA”, in 2022 IEEE 13th Latin American Symposium on Circuits and Systems (LASCAS), Puerto Varas, Chile, 1-4 March, 2022.
  7. S. Jakhodia and B. Jajodia , “Numerical Methods for Solving High-Order Mathematical Problems Using Quantum Linear System Algorithm on IBM QISKit Platform”, in 2022 IEEE 3rd International Conference on Innovative Trends in Information Technology (ICITIIT), Virtual Mode, pp. 1-7, 12-13 February, 2022
  8. J. Bajaj and B. Jajodia , “Efficient Hardware Implementation of High-Speed Recursive Vedic Squaring Architecture on FPGA”, in 2021 IEEE International Conference on Electrical, Computer and Energy Technologies (ICECET), Cape Town, South Africa, pp. 1-6, 9-10 December, 2021
  9. M. Thakare, P. Yash, D. Chakraborty and B. Jajodia , “Efficient Hardware Implementation of Cube Architecture using Yavadunam Sutra on FPGA," in 2021 IEEE 64th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 373-376, 2021
  10. R. Thombre and B. Jajodia , “Experimental Analysis of Attacks on RSA & Rabin Cryptosystems using Quantum Shor’s Algorithm," in Proceedings of International Conference on Women Researchers in Electronics and Computing (WREC), AIJR Proceedings, pp. 581-590, April 22-24, 2021 (Best Paper Award)
  11. J. Bajaj and B. Jajodia , “Squaring Technique using Vedic Mathematics," in Proceedings of International Conference on Women Researchers in Electronics and Computing (WREC), AIJR Proceedings, pp. 591-600, April 22–24, 2021,
  12. B. Jajodia , S.R. Ahamed and A. Mahanta, “Demodulation techniques for IEEE 802.15.6 IR-UWB DBPSK WBAN transceivers”, in IEEE 3rd International Conference on Smart Instrumentation, Measurement and Applications (ICSIMA), Putrajaya Marriott Hotel, Malaysia, 2015, India, pp. 1-5, Nov. 2015
  13. B. Jajodia , S.R. Ahamed and A. Mahanta, “PPM Demodulation Schemes for IEEE 802.15.6 IR-UWB WBAN Receivers”, in IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems (SPICES), NIT Calicut, India, pp. 1-5, Feb. 2015
  14. B. Jajodia , A. Mahanta and S.R. Ahamed, “A Six-Segment SRRC Pulse Generator for IEEE 802.15.6 WBAN Standard”, in BODYNETS 2014 - 9th International Conference on Body Area Networks, Senate House, London, Great Britain, pp. 46-49, Nov. 2014

Book Chapters
  1. S. Jakhodia, D. Singh and B. Jajodia , “Experimental Evaluation of QFT Adders on IBM QX Hardware”,In: Singh, P.K., Kolekar, M.H., Tanwar, S., Wierzchoń, S.T., Bhatnagar, R.K. (eds) 2nd International Conference on Emerging Technologies for Computing, Communication and Smart Cities (ETCCS), Lecture Notes in Electrical Engineering, vol. 875, pp. 419-435, Springer, Singapore, 20th April 2022, Print ISBN: 978-981-19-0283-3, Online ISBN: 978-981-19-0284-0, 2022
  2. D. Singh, S. Jakhodia and B. Jajodia , “Experimental Evaluation of Adder Circuits on IBM QX Hardware”, In: Smys S., Balas V.E., Palanisamy R. (eds) Inventive Computation and Information Technologies (ICICIT). Lecture Notes in Networks and Systems, vol. 336. pp. 333-347, Springer, Singapore, 01st January 2022, Print ISBN: 978-981-16-6722-0, Online ISBN: 978-981-16-6723-7, 2022

Posters
  1. D. Pandey, V. Mishra, S. Singh, S. Satapathy and B. Jajodia , "HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications", in 28th IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC) Student Research Symposium (SRS), Bengaluru, Karnataka, 17-18 December, 2021 (Best Poster Award)

Others
  1. P. Das and B. Jajodia , "Design Optimization of Analog Circuit using Multi-Objective Genetic Algorithm and SPICE Framework" in North-East Research Conclave, Indian Institute of Technology Guwahati, 20-22 May, 2022 (Technical Presentation on Extended Abstract)

Dr. Babita Jajodia

Assistant Professor (ECE)

PhD (IIT Guwahati)

Email:

babita@iiitg.ac.in

Contact:

9707118084